PCIMX512CJM6C datasheet(66/184 Pages) FREESCALE

66 / 184 page

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

3.7.4

FEC AC Timing Parameters

This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC

is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver

interface and transceiver function are required to complete the interface to the media. The FEC supports

the 10/100 Mbps MII (18 pins in total) and the 10 Mbps-only 7-wire interface, which uses 7 of the MII

pins, for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, refer to the

i.MX51 Reference Manual.

This section describes the AC timing specifications of the FEC. The MII signals are compatible with

transceivers operating at a voltage of 3.3 V.

3.7.4.1

MII Receive Signal Timing

The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and

FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of

25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must

exceed twice the FEC_RX_CLK frequency. Table 57 lists the MII receive channel signal timing

parameters and Figure 40 shows MII receive signal timings.

SD7

eSDHC Input Setup Time

tISU

2.5

—

SD8

eSDHC Input Hold Time

tIH

2.5

—

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2 In normal speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock

frequency can be any value between 0

–50 MHz.

3 In normal speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0

–52 MHz.

4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

Table 57. MII Receive Signal Timing

Num

Characteristic1

1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.

Min

Max

Unit

FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup

—

FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold

—

FEC_RX_CLK pulse width high

35%

65%

FEC_RX_CLK period

FEC_RX_CLK pulse width low

35%

65%

FEC_RX_CLK period

Table 56. eSDHCv2 Interface Timing Specification (continued)

Parameter

Symbols

Min

Max

Unit

PCIMX512CJM6C Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc

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