PCIMX515CJM6C datasheet(135/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

135

Preliminary—Subject to Change Without Notice

3.7.18

USB Parallel Interface Timing

Electrical and timing specifications of Parallel Interface are presented in the subsequent sections.

Figure 101. USB Transmit/Receive Waveform in Parallel Mode

Table 104. Signal Definitions—Parallel Interface (Normal ULPI)

Name

Direction

Signal Description

USB_Clk

Interface clock. All interface signals are synchronous to Clock.

USB_Data[7:0]

I/O

Bi-directional data bus, driven low by the link during idle. Bus

ownership is determined by Dir.

USB_Dir

Direction. Control the direction of the Data bus.

USB_Stp

Out

Stop. The link asserts this signal for 1 clock cycle to stop the data

stream currently on the bus.

USB_Nxt

Next. The PHY asserts this signal to throttle the data.

Table 105. USB Timing Specification for ULPI Parallel Mode

Parameter

Min

Max

Unit

Conditions /

Reference Signal

US15

Setup Time (Dir, Nxt in, Data in)

—

10 pF

US16

Hold Time (Dir, Nxt in, Data in)

—

10 pF

US17

Output delay Time (Stp out, Data out)

—

10 pF

USB_Stp

USB_Dir/Nxt

US17

US16

USB_Data

US15

US16

US15

US17

USB_Clk

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