ADN4604ASVZ datasheet(25/40 Pages) AD

25 / 40 page

ADN4604

Rev. 0 | Page 25 of 40

I2C DATA READ

To read data from the ADN4604 register set, a microcontroller,

or any other I2C master must send the appropriate control

signals to the ADN4604 slave device. The steps are listed below;

the signals are controlled by the I2C master, unless otherwise

specified. A diagram of the procedure is shown in Figure 47.

Send a start condition (while holding the SCL line high,

pull the SDA line low).

Send the ADN4604 part address (seven bits) whose upper

five bits are the static value b10010 and whose lower two

bits are controlled by the input pins ADDR1 and ADDR0.

This transfer should be MSB first.

Send the write indicator bit (0).

Wait for the ADN4604 to acknowledge the request.

Send the register address (eight bits) from which data is to

be read. This transfer should be MSB first. The register

address is kept in memory in the ADN4604 until the part

is reset or the register address is written over with the same

procedure (Step 1 to Step 6).

Wait for the ADN4604 to acknowledge the request.

Send a repeated start condition (while holding the SCL line

high, pull the SDA line low).

Send the ADN4604 part address (seven bits) whose upper

five bits are the static value b10010 and whose lower two

bits are controlled by the input pins ADDR1 and ADDR0.

This transfer should be MSB first.

Send the read indicator bit (1).

10. Wait for the ADN4604 to acknowledge the request.

11. The ADN4604 then serially transfers the data (eight bits)

held in the register indicated by the address set in Step 5.

12. Acknowledge the data.

13. Do one or more of the following:

Send a stop condition (while holding the SCL line high

pull the SDA line high) and release control of the bus.

Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue

with Step 2 of the write procedure (see the I2C Data

Write section) to perform a write.

Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue

with Step 2 of this procedure to perform a read from

another address.

Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue

with Step 8 of this procedure to perform a read from

the same address.

The ADN4604 read process is shown in Figure 47. The SCL

signal is shown along with a general read operation and a

specific example. In the example, Data 0x49 is read from

Address 0x6D of an ADN4604 part with a part address of 0x4B.

The part address is seven bits wide and is composed of the

ADN4604 static upper five bits (b10010) and the pin program-

mable lower two bits (ADDR1 and ADDR0). In this example,

the ADDR1 and ADDR0 bits are set to b01. In Figure 47, the

corresponding step number is visible in the circle under the

waveform. The SCL line is driven by the I2C master and never

by the ADN4604 slave. As for the SDA line, the data in the

shaded polygons is driven by the ADN4604, whereas the data in

the nonshaded polygons is driven by the I2C master. The end

phase case shown is that of 13a.

Note that the SDA line only changes when the SCL line is low,

except for the case of sending a start, stop, or repeated start

condition, as in Step 1, Step 7, and Step 13. In Figure 47, A is

the same as ACK in Figure 46. Equally, Sr represents a repeated

start where the SDA line is brought high before SCL is raised.

SDA is then dropped while SCL is still high.

SCL

SDA

EXAMPLE

b10010

DATA

STOP

START

ADDR

[1:0]

ADDR

[1:0]

b10010

13a

Figure 47. I2C Read Diagram

ADN4604ASVZ Datasheet(PDF) 25 Page - Analog Devices

ADN4604ASVZ Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL