ADP1043A datasheet(13/72 Pages) AD

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ADP1043A

Rev. 0 | Page 13 of 72

VOLTAGE SENSE AND CONTROL LOOP

Multiple voltage sense inputs on the ADP1043A are used for the

monitoring, control, and protection of the power supply output.

The voltage information is available through the I2C interface.

All voltage sense points can be calibrated digitally to remove

any errors due to external components. This calibration can be

performed in the production environment, and the settings can

be stored in the EEPROM of the ADP1043A (see the Power

Supply Calibration and Trim section for more information).

The update rate of the ADC from a control loop standpoint

is set to the switching frequency. Therefore, if the switching

frequency is set to 100 kHz, the ADC outputs a signal every

100 kHz to the control loop. Because the Σ-Δ modulators of the

ADC sample at 1.6 MHz, the output of the ADC is the average

of the 16 readings taken during the 1.6 MHz time frame.

For voltage monitoring, the VS1, VS2, and VS3 voltage value

registers are updated every 10 ms. The ADP1043A stores every

ADC sample for 10 ms and then outputs the average value at the

end of the 10 ms period. Therefore, if these registers are read at

least every 10 ms, a true average value is read. The same applies

to the CS1 and CS2 current readings.

For the control loop, the high speed signal always comes from

the VS1 high speed ADC. The low speed signal normally comes

from the VS3 low speed ADC. However, during soft start or in

response to a load OVP or other fault condition, the ADP1043A

can switch its low speed regulating point from VS3 to VS1.

VS1

VS3+

VS3–

VS2

ADC

PGND

VS3

VS2

VS1

LOW

SPEED

12 BITS

DIGITAL

FILTER

HIGH

FREQUENCY

FEEDBACK

LOOP

LOW FREQUENCY

FEEDBACK LOOP

12V

11k

Ω

LOAD

11k

Ω

11k

Ω

12V

ADC

VS1

HIGH

SPEED

6 BITS

ADC

Figure 13. Voltage Sense Configuration

VS1 Operation (VS1)

VS1 is used for the monitoring and protection of the power

supply voltage at the output of the LC stage, upstream of the

OrFET. This is also the high frequency feedback loop for the

power supply. The VS1 sense point on the power rail needs an

external resistor divider to bring the nominal common-mode

signal to 1 V at the VS1 pin (see Figure 13). The resistor divider

is necessary because the ADP1043A VS1 ADC input range is

0 V to 1.55 V. This divided-down signal is internally fed into a

high speed and a low speed Σ-Δ ADC. The output of the VS1

ADCs goes to the digital filter.

The high speed ADC has a 2 MHz bandwidth and is run from

a 25 MHz clock. It has a range of ±18 mV. When the sampling

rate is 200 kHz, there is 0.6 mV (two LSBs) of quantization noise.

Increasing the sampling rate to 400 kHz increases the quanti-

zation noise to 1.2 mV.

In the event of a load overvoltage condition, the power supply

is regulated from the VS1 sense point, rather than from the

VS3 sense point.

VS2 Operation (VS2)

VS2 is typically used for the monitoring and protection of the

output of the power supply, downstream of the OrFET. It is

used with VS1 to control the OrFET gate drive turn-on. The

VS2 sense point on the power rail needs an external resistor

divider to bring the nominal common-mode signal to 1 V at

the VS2 pin (see Figure 13). The resistor divider is necessary

because the ADP1043A VS2 ADC input range is 0 V to 1.55 V.

This divided-down signal is internally fed into an ADC. The

output of the VS2 ADC goes to the VS2 voltage value register

(Register 0x16).

VS3 Operation (VS3+, VS3−)

VS3± is used for the monitoring and protection of the remote

load voltage. It is a fully differential input. This is the main

feedback sense point for the power supply control loop. The

VS3 sense point on the power rail needs an external resistor

divider to bring the nominal common-mode signal to 1 V at

the VS3± pins (see Figure 13). The resistor divider is necessary

because the ADP1043A VS3 ADC input range is 0 V to 1.55 V.

This divided-down signal is internally fed into an ADC. The

output of the VS3 ADC goes to the digital filter.

ADCs

The ADP1043A includes several ADCs. The high speed ADC is

described in the VS1 Operation (VS1) section. The other ADCs

are low speed, high resolution. They have a 1 kHz bandwidth

and 12-bit resolution. Each ADC has its own voltage reference

for added protection from potential failure. The digital output

of each ADC is readable through the appropriate value register.

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