56F8167 datasheet(152/182 Pages) FREESCALE

152 / 182 page

56F8367 Technical Data, Rev. 9

152

Freescale Semiconductor

Preliminary

Figure 10-6 Asynchronous Reset Timing

Figure 10-7 External Interrupt Timing (Negative Edge-Sensitive)

IRQA, IRQB Assertion to General Purpose

Output Valid, caused by first instruction

execution in the interrupt service routine

tIG

18T

—

10-8

tIG - FAST

14T

—

Delay from IRQA Assertion (exiting Wait) to

External Data Memory Access4

tIRI

22T

—

10-9

tIRI -FAST

18T

—

Delay from IRQA Assertion to External Data

Memory Access (exiting Stop)

tIF

22T

—

10-10

tIF - FAST

18T

—

IRQA Width Assertion to Recover from Stop

State5

tIW

1.5T

—

10-10

1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and

Stop modes), T = 125ns.

2. Parameters listed are guaranteed by design.

3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 221T.

4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This

is not the minimum required so that the IRQA interrupt is accepted.

5. The interrupt instruction fetch is visible on the pins only in Mode 3.

Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2

Characteristic

Symbol

Typical

Min

Typical

Max

Unit

See Figure

First Fetch

tRA

tRAZ

tRDA

A0–A15,

D0–D15

PS, DS,

RD, WR

RESET

First Fetch

IRQA,

IRQB

tIRW

56F8167 Datasheet(PDF) 152 Page - Freescale Semiconductor, Inc

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