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56F8167 Datasheet(PDF) 150 Page - Freescale Semiconductor, Inc |
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56F8167 Datasheet(HTML) 150 Page - Freescale Semiconductor, Inc |
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150 / 182 page ![]() 56F8367 Technical Data, Rev. 9 150 Freescale Semiconductor Preliminary Figure 10-5 External Memory Interface Timing Note: When multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative. Table 10-16 External Memory Interface Timing Characteristic Symbol Wait States Configuration DM Wait States Controls Unit Address Valid to WR Asserted tAWR WWS=0 -2.076 0.50 WWSS ns WWS>0 -1.795 0.75 + DCAOE WR Width Asserted to WR Deasserted tWR WWS=0 -0.094 0.25 + DCAOE WWS ns WWS>0 -0.012 0 Data Out Valid to WR Asserted tDWR WWS=0 -9.321 0.25 + DCAEO WWSS ns WWS=0 -1.160 0.00 WWS>0 -8.631 0.50 WWS>0 -0.879 0.25 + DCAOE Valid Data Out Hold Time after WR Deasserted tDOH -2.086 0.25 + DCAEO WWSH ns Valid Data Out Set-Up Time to WR Deasserted tDOS -0.563 0.25 + DCAOE WWS,WWSS ns -8.315 0.50 Valid Address after WR Deasserted tWAC -3.432 0.25 + DCAEO WWSH ns RD Deasserted to Address Invalid tRDA -1.780 0.00 RWSH ns tDRD tRDD tAD tDOH tDOS tDWR tRDWR tWAC tWRRD tWR tAWR tWRWR tARDD tRDA tRDRD tRD tARDA Data Out Data In A0-Axx,CS RD WR D0-D15 Note: During read-modify-write instructions and internal instructions, the address lines do not change state. |
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