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AT90SCR100 Datasheet(PDF) 227 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 227 Page - ATMEL Corporation |
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227 / 433 page ![]() 227 TPR0327AY–SMS–30Jan09 AT90SCR100 • Bit 4 - CRC16 : CRC16 Error Set by hardware when a CRC16 error has been detected. Shall be cleared by software. Setting by software has no effect. • Bit 3 - PTIMEOUT - Pipe Time-out Error Set by hardware when a time-out error has been detected. Shall be cleared by software. Setting by software has no effect. • Bit 2 - PID - PID Error Set by hardware when a PID error has been detected. Shall be cleared by software. Setting by software has no effect. • Bit 1 - DATAPID - Data PID Error Set by hardware when a data PID error has been detected. Shall be cleared by software. Setting by software has no effect. • Bit 0 - DATATGL - Bad Data Toggle Set by hardware when a data toggle error has been detected. Shall be cleared by software. Setting by software has no effect. 17.7.17 UPINTX - USB Pipe INTerrupt Register for Pipe X Set UPNUM register to point to the relevant Pipe before using the UPINTX register. • Bit 7 - FIFOCON : FIFO Control For OUT and SETUP Pipe: Set by hardware when the current bank is free, at the same time than TXOUT or TXSTP. Clear to send the FIFO data. Setting by software has no effect. For IN Pipe: Set by hardware when a new IN message is stored in the current bank, at the same time than RXIN. Clear to free the current bank and to switch to the following bank. Setting by software has no effect. • Bit 6 - NAKEDI : NAK Handshake received Set by hardware when a NAK has been received on the current bank of the Pipe. This triggers an interrupt if the NAKEDE bit is set in the UPIENX register. Shall be clear to handshake the interrupt. Setting by software has no effect. • Bit 5 - RWAL : Read/Write Allowed Bit 7 6 543 2 1 0 $00A6 FIFOCON NAKEDI RWAL PERRI TXSTPI TXOUTI RXSTALLI RXINI UPINTX Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x00 |
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