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AT90SCR100 Datasheet(PDF) 229 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 229 Page - ATMEL Corporation |
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229 / 433 page ![]() 229 TPR0327AY–SMS–30Jan09 AT90SCR100 17.7.18 UPIENX - USB Pipe Interrupt ENable Register for Pipe X Set UPNUM register to point to the relevant Pipe before using the UPIENX register. • Bit 7 - FLERRE : Flow Error Interrupt enable Set to enable the OVERFI and UNDERFI interrupts. Clear to disable the OVERFI and UNDERFI interrupts. • Bit 6 - NAKEDE : NAK Handshake Received Interrupt Enable Set to enable the NAKEDI interrupt. Clear to disable the NAKEDI interrupt. • Bit 5 - Res : Reserved The value read from these bits is always 0. Do not set these bits. • Bit 4 - PERRE : PIPE Error Interrupt Enable Set to enable the PERRI interrupt. Clear to disable the PERRI interrupt. • Bit 3 - TXSTPE : SETUP Bank ready Interrupt Enable Set to enable the TXSTPI interrupt. Clear to disable the TXSTPI interrupt. • Bit 2 - TXOUTE : OUT Bank ready Interrupt Enable Set to enable the TXOUTI interrupt. Clear to disable the TXOUTI interrupt. • Bit 1 - RXSTALLE : STALL Received Interrupt Enable Set to enable the RXSTALLI interrupt. Clear to disable the RXSTALLI interrupt. • Bit 0 - RXINE : IN Data received Interrupt Enable Set to enable the RXINI interrupt. Clear to disable the RXINI interrupt. 17.7.19 UPDATX - USB Pipe Data Register for Pipe X Set UPNUM register to point to the relevant Pipe before using the UPDATX register. Bit 7 6 5 4 3 2 1 0 $00AE FLERRE NAKEDE - PERRE TXSTPE TXOUTE RXSTALLE RXINE UPIENX Read/write R/W R/W R R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x00 Bit 7 6 5 4 3 2 1 0 $00AF PDAT [7..0] UPDATX Read/write R/W R/W R R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x00 |
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