AT90SCR100 datasheet(233/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

chronous, Master synchronous and Slave synchronous mode. The UMSEL0 bit in USART

Control and Status Register C (UCSR0C) selects between asynchronous and synchronous

operation. Double Speed (asynchronous mode only) is controlled by the U2X0 found in the

UCSR0A Register. When using synchronous mode (UMSEL0 = 1), the Data Direction Register

for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or

external (Slave mode). The XCK pin is only active when using synchronous mode.

Figure 18-2.

Clock Generation Logic, Block Diagram

Signal description:

txclk

Transmitter clock (Internal Signal).

rxclk

Receiver base clock (Internal Signal).

xcki

Input from XCK pin (internal Signal). Used for synchronous slave

operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

OSC

UART Block clock: clkIO

18.4.1

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of

operation. The description in this section refers to Figure 18-2.

The USART Baud Rate Register (UBRR0) and the down-counter connected to it function as a

programmable prescaler or baud rate generator. The down-counter, running at system clock

(fosc), is loaded with the UBRR0 value each time the counter has counted down to zero or when

the UBRRL0 Register is written. A clock is generated each time the counter reaches zero. This

clock is the baud rate generator clock output (= fosc/(UBRR0+1)). The Transmitter divides the

baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-

put is used directly by the Receiver’s clock and data recovery units. However, the recovery units

use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the

UMSEL0, U2X0 and DDR_XCK bits.

Prescaling

Down-Counter

UBRR

fosc

UBRR+1

Sync

Clk

or XCK

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK

rxclk

Edge

Detector

UCPOL

AT90SCR100 Datasheet(PDF) 233 Page - ATMEL Corporation

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