AT90SCR100 datasheet(236/433 Pages) ATMEL

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AT90SCR100

is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can

be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 18-4 illustrates the possible combinations of the frame formats. Bits inside brackets are

optional.

Figure 18-4.

Frame Formats

Start bit, always low.

(n)

Data bits (0 to 8).

Parity bit. Can be odd or even.

Stop bit, always high.

IDLE

No transfers on the communication line (RxD0 or TxD0). An IDLE line

must be

high.

The frame format used by the USART is set by the UCSZ02:0, UPM01:0 and USBS0 bits in

UCSR0B and UCSR0C. The Receiver and Transmitter use the same setting. Note that changing

the setting of any of these bits will corrupt all ongoing communication for both the Receiver and

Transmitter.

The USART Character SiZe (UCSZ02:0) bits select the number of data bits in the frame. The

USART Parity mode (UPM01:0) bits enable and set the type of parity bit. The selection between

one or two stop bits is done by the USART Stop Bit Select (USBS0) bit. The Receiver ignores

the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the

first stop bit is zero.

18.5.1

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the

result of the exclusive or is inverted. The relation between the parity bit and data bits is as

follows::

even

Parity bit using even parity

Podd

Parity bit using odd parity

Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

18.6

USART Initialization

The USART has to be initialized before any communication can take place. The initialization pro-

cess normally consists of setting the baud rate, setting frame format and enabling the

Transmitter or the Receiver depending on the usage. For interrupt driven by USART operation,

[5]

[6]

[7]

[8]

[P]

Sp1 [Sp2]

(St / IDLE)

(IDLE)

FRAME

even

–

… d3 d2 d1 d0 0

odd

⊕⊕⊕

⊕⊕

⊕

–

… d3 d2 d1 d0 1

⊕⊕⊕

⊕⊕

⊕

AT90SCR100 Datasheet(PDF) 236 Page - ATMEL Corporation

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