AT90SCR100 datasheet(243/433 Pages) ATMEL

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AT90SCR100

18.8.3

Receive Compete Flag and Interrupt

The USART Receiver has one flag that indicates the Receiver state.

The Receive Complete (RXC0) Flag indicates if there are unread data present in the receive buf-

fer. This flag is one when unread data exist in the receive buffer, and zero when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN0 = 0),

the receive buffer will be flushed and consequently the RXC0 bit will become zero.

When the Receive Complete Interrupt Enable (RXCIE0) in UCSR0B is set, the USART Receive

Complete interrupt will be executed as long as the RXC0 Flag is set (provided that global inter-

rupts are enabled). When interrupt-driven data reception is used, the receive complete routine

must read the received data from UDR0 in order to clear the RXC0 Flag, otherwise a new inter-

rupt will occur once the interrupt routine terminates.

18.8.4

Receiver Error Flags

The USART Receiver has three Error Flags: Frame Error (FE0), Data OverRun (DOR0) and

Parity Error (UPE0). All can be accessed by reading UCSR0A. Common for the Error Flags is

that they are located in the receive buffer together with the frame for which they indicate the

error status. Due to the buffering of the Error Flags, the UCSR0A must be read before the

receive buffer (UDR0), since reading the UDR0 I/O location changes the buffer read location.

Another equality for the Error Flags is that they can not be altered by software doing a write to

the flag location. However, all flags must be set to zero when the UCSR0A is written for upward

compatibility of future USART implementations. None of the Error Flags can generate interrupts.

The Frame Error (FE0) Flag indicates the state of the first stop bit of the next readable frame

stored in the receive buffer. The FE0 Flag is zero when the stop bit was correctly read (as one),

and the FE0 Flag will be one when the stop bit was incorrect (zero). This flag can be used for

detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE0

Flag is not affected by the setting of the USBS0 bit in UCSR0C since the Receiver ignores all,

except for the first, stop bits. For compatibility with future devices, always set this bit to zero

when writing to UCSR0A.

The Data OverRun (DOR0) Flag indicates data loss due to a receiver buffer full condition. A

Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait-

ing in the Receive Shift Register, and a new start bit is detected. If the DOR0 Flag is set there

was one or more serial frame lost between the frame last read from UDR0, and the next frame

read from UDR0. For compatibility with future devices, always write this bit to zero when writing

to UCSR0A. The DOR0 Flag is cleared when the frame received was successfully moved from

the Shift Register to the receive buffer.

The Parity Error (UPE0) Flag indicates that the next frame in the receive buffer had a Parity

Error when received. If Parity Check is not enabled the UPE0 bit will always be read zero. For

compatibility with future devices, always set this bit to zero when writing to UCSR0A. For more

details see “Parity Bit Calculation” on page 236 and “Parity Checker” on page 243.

18.8.5

Parity Checker

The Parity Checker is active when the high USART Parity mode (UPM01) bit is set. Type of Par-

ity Check to be performed (odd or even) is selected by the UPM00 bit. When enabled, the Parity

Checker calculates the parity of the data bits in incoming frames and compares the result with

the parity bit from the serial frame. The result of the check is stored in the receive buffer together

AT90SCR100 Datasheet(PDF) 243 Page - ATMEL Corporation

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