AT90SCR100 datasheet(244/433 Pages) ATMEL

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AT90SCR100

with the received data and stop bits. The Parity Error (UPE0) Flag can then be read by software

to check if the frame had a Parity Error.

The UPE0 bit is set if the next character that can be read from the receive buffer had a Parity

Error when received and the Parity Checking was enabled at that point (UPM01 = 1). This bit is

valid until the receive buffer (UDR0) is read.

18.8.6

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing

receptions will therefore be lost. When disabled (i.e., the RXEN0 is set to zero) the Receiver will

no longer override the normal function of the RxD0 port pin. The Receiver buffer FIFO will be

flushed when the Receiver is disabled. Remaining data in the buffer will be lost

18.8.7

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be

emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal

operation, due to for instance an error condition, read the UDR0 I/O location until the RXC0 Flag

is cleared. The following code example shows how to flush the receive buffer.

Note:

1. See “About Code Examples” on page 11.

18.9

Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data

reception. The clock recovery logic is used for synchronizing the internally generated baud rate

clock to the incoming asynchronous serial frames at the RxD0 pin. The data recovery logic sam-

ples and low pass filters each incoming bit, thereby improving the noise immunity of the

Receiver. The asynchronous reception operational range depends on the accuracy of the inter-

nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

18.9.1

Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 18-5

illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times

the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-

izontal arrows illustrate the synchronization variation due to the sampling process. Note the

larger time variation is obtained when using the Double Speed mode (U2X0 = 1) of operation.

Assembly Code Example(1)

USART_Flush:

sbis

UCSR0A, RXC0

ret

r16, UDR0

rjmp

USART_Flush

C Code Example(1)

void

USART_Flush( void )

{

unsigned char

dummy;

while

( UCSR0A & (1<<RXC0) ) dummy = UDR0;

}

AT90SCR100 Datasheet(PDF) 244 Page - ATMEL Corporation

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