AT90SCR100 datasheet(263/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

19.7.2

UCSR0A – USART MSPIM Control and Status Register 0 A

• Bit 7 – RXC0: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXC0 bit will become zero. The RXC0 Flag can be

used to generate a Receive Complete interrupt (see description of the RXCIE0 bit).

• Bit 6 – TXC0: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDR0). The TXC0 Flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXC0 Flag can generate a Transmit Complete interrupt (see

description of the TXCIE0 bit).

• Bit 5 – UDRE0: USART Data Register Empty

The UDRE0 flag indicates if the transmit buffer (UDR0) is ready to receive new data. If UDRE0 is

one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag can generate a

Data Register Empty interrupt (see description of the UDRIE0 bit).

UDRE0 is set after a reset to indicate that the Transmitter is ready.

• Bit 4..0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSR0A is written.

19.7.3

UCSR0B – USART MSPIM Control and Status Register 0 B

• Bit 7 – RXCIE0: RX Complete Interrupt Enable 0

Writing this bit to one enables interrupt on the RXC0 Flag. A USART Receive Complete interrupt

will be generated only if the RXCIE0 bit is written to one, the Global Interrupt Flag in SREG is

written to one and the RXC0 bit in UCSR0A is set.

• Bit 6 – TXCIE0: TX Complete Interrupt Enable 0

Writing this bit to one enables interrupt on the TXC0 Flag. A USART Transmit Complete interrupt

will be generated only if the TXCIE0 bit is written to one, the Global Interrupt Flag in SREG is

written to one and the TXC0 bit in UCSR0A is set.

• Bit 5 – UDRIE0: USART Data Register Empty Interrupt Enable 0

Bit

7654

$0000C0

RXC0

TXC0

UDRE0

UCSR0A

Read/write

R/W

Initial value

0010

0x20

Bit

7654

$0000C1

RXCIE0

TXCIE0

UDRIE0

RXE0

TXE0

UCSR0B

Read/write

R/W

Initial value

0000

0x00

AT90SCR100 Datasheet(PDF) 263 Page - ATMEL Corporation

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