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AT90SCR100 Datasheet(PDF) 265 Page - ATMEL Corporation

Part # AT90SCR100
Description  8-bit Microcontroller for Smart Card Readers
PDF  433 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90SCR100 Datasheet(HTML) 265 Page - ATMEL Corporation

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265
TPR0327AY–SMS–30Jan09
AT90SCR100
• Bit 1 - UCPHA0: Clock Phase
The UCPHA0 bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCK0. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOL0: Clock Polarity
The UCPOL0 bit sets the polarity of the XCK0 clock. The combination of the UCPOL0 and
UCPHA0 bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing section page 4 for details.
19.7.5
UBRR0L and UBRR0H –USART MSPIM Baud Rate Registers
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See “UBRR0L and UBRR0H – USART Baud Rate Registers” on page 253.
19.8
AVR USART MSPIM vs. AVR SPI
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
• Master mode timing diagram.
• The UCPOL0 bit functionality is identical to the SPI CPOL bit.
• The UCPHA0 bit functionality is identical to the SPI CPHA bit.
• The UDORD0 bit functionality is identical to the SPI DORD bit.
However, since the USART in MSPIM mode reuses the USART resources, the use of the
USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of
the control register bits, and that only master operation is supported by the USART in MSPIM
mode, the following features differ between the two modules:
• The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no
buffer.
• The USART in MSPIM mode receiver includes an additional buffer level.
• The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.
• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is
achieved by setting UBRR0 accordingly.
• Interrupt timing is not compatible.
• Pin control differs due to the master only operation of the USART in MSPIM mode.
A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 19-4 on page
265.
Table 19-4.
Comparison of USART in MSPIM mode and SPI pins.
USART_MSPIM
SPI
Comment
TxD0
MOSI
Master Out only
RxD0
MISO
Master In only
XCK0
SCK
(Functionally identical)
(N/A)
SS
Not supported by USART in MSPIM



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