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AT90SCR100 Datasheet(PDF) 286 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 286 Page - ATMEL Corporation |
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286 / 433 page  286 TPR0327AY–SMS–30Jan09 AT90SCR100 21.3 HSSS line Functionality 21.3.1 Slave Mode When the HSSPI is configured as a Slave (HSSPICFG.MSTR bit cleared), the Slave Select (HSSS) line is driven by the master device. The HSSS has no effect on the HSSPI logic. It is the software’s responsibility to manage the HSSS level. 21.3.2 Master Mode When the HSSPI is configured as a Master (HSSPICFG.MSTR bit set), the HSSS line is used to select the slave. 21.4 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 21-9 and Figure 21-10. Figure 21-9. SPI Transfer Format with CPHA = 0 Figure 21-10. SPI Transfer Format with CPHA = 1 |
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