AT90SCR100 datasheet(382/433 Pages) ATMEL

382 / 433 page

382

TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 29-1.

Serial Programming and Verify

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

29.6.2

Serial Programming Algorithm

When writing serial data to the AT90SCR100, data is clocked on the rising edge of SCK.

When reading data from the AT90SCR100, data is clocked on the falling edge of SCK. See Fig-

ure 29-3 for timing details.

To program and verify the AT90SCR100 in the serial programming mode, the following

sequence is recommended (See four byte instruction formats in Table 29-11):

1. Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of syn-

chronization. When in sync. the second byte (0x53), will echo back when issuing the

third byte of the Programming Enable instruction. Whether the echo is correct or not, all

four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give

RESET a positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at

a time by supplying the 7 LSB of the address and data together with the Load Program

Memory Page instruction. To ensure correct loading of the page, the data low byte

must be loaded before data high byte is applied for a given address. The Program

Memory Page is stored by loading the Write Program Memory Page instruction with the

VCC

GND

XT AL1

SCK

MISO

MOSI

RESET

+1.8 - 5.5V

AVCC

+1.8 - 5.5V

(2)

AT90SCR100 Datasheet(PDF) 382 Page - ATMEL Corporation

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