AT90SCR100 datasheet(411/433 Pages) ATMEL

411 / 433 page

411

TPR0327AY–SMS–30Jan09

AT90SCR100

31.4

Clocks

31.4.1

XTAL1 : External Clock In TBC/TBD

This clock relates to Core and System clock. See “Clock Sources” on page 33.

31.4.2

Calibrated Internal RC Oscillator Accuracy

This clock concerns the Flash/Eeprom specific clock. See “Internal RC Oscillator” on page 37.

31.5

Communication Interfaces

31.5.1

2-wire Serial Interface Characteristics TBC/TBD

Table 31-3 describes the requirements for devices connected to the 2-wire Serial Bus. The

AT90SCR100 2-wire Serial Interface meets or exceeds these requirements under the noted

conditions.

Timing symbols refer to Figure 31-1.

Table 31-1.

XTAL1 = XIN Clock Electrical Characteristics

Symbol

Parameter

Min.

Max.

Units

1/tCPXIN

XIN Clock Frequency

MHz

tCHXIN

XIN Clock High Half-Period

0.4 x tCPXIN

tCLCX

XIN Clock Low HAlf-Period

0.4 x tCPXIN

CIN

XIN Input Capacitance

RIN

XIN Pulldown Resistor

Table 31-2.

Calibration Accuracy of Internal RC Oscillator

Frequency

Temperature

Calibration Accuracy

Factory Calibration

10.0 MHz

⋅C±5%

User Calibration

9.5 - 10.5 MHz

2.4V - 5.5V

-40

⋅C - 85⋅C±1%

Table 31-3.

2-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

VIL

Input Low-voltage

-0.5

0.3 VCC

VIH

Input High-voltage

0.6 VCC

VCC + 0.5

Vhys

(1)

Hysteresis of Schmitt Trigger Inputs

0.05 VCC

(2)

–V

VOL

(1)

Output Low-voltage

3 mA sink current

0.4

tr(1)(8)

Rise Time for both SDA and SCL

20 + 0.1Cb(2)(3)

300

tof

(1)(8)

Output Fall Time from VIHmin to VILmax

10 pF < Cb < 400 pF

(3)

20 + 0.1Cb

(2)(3)

250

tSP

(1)(8)

Spikes Suppressed by Input Filter

50(2)

Ci(1)(8)

Capacitance for each I/O Pin

–

fSCL

SCL Clock Frequency

fCK

(4)> max(16f

SCL, 250kHz)

(5)

0400

kHz

tHD;STA

Hold Time (repeated) START Condition

fSCL ≤ 100 kHz

4.0

–

μs

fSCL > 100 kHz

0.6

–

μs

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