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AT90SCR100 Datasheet(PDF) 413 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 413 Page - ATMEL Corporation |
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413 / 433 page ![]() 413 TPR0327AY–SMS–30Jan09 AT90SCR100 31.5.3 SPI Timing Characteristics TBC/TBD See Figure 31-2 and Figure 31-3 for details. Notes: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12 MHz - 3 tCLCL for fCK > 12 MHz 2. These values are for information only. They are not tested to production test flow. They are deduced from characterization session. Figure 31-2. SPI Interface Timing Requirements (Master Mode) Table 31-4. SPI Timing Parameters(2) Description Mode Min Typ Max 1 SCK period Master See Table 20-4 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5Hold Master 10 6 Out to SCK Master 0.5 • tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low(1) Slave 2 • tck 12 Rise/Fall time Slave 1600 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 20 MO SI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 61 22 3 45 8 7 |
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