HT45R35V datasheet(23/42 Pages) HOLTEK

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HT45R35V

Rev. 1.00

January 15, 2009

V D D

I / O

O P 0 ~ O P 7

T M R f o r P A 2 o n l y

I N T 0 f o r P A 0 o n l y

I N T 1 f o r P A 1 o n l y

S y s t e m W a k e - u p

( P A o n l y )

R e a d D a t a R e g i s t e r

C o n t r o l B i t

P u l l - h i g h

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

C K

Input/Output Ports

There are 9 bidirectional input/output lines in the

microcontroller, all located within port PA and PB. All of

these I/O ports can be used for input and output opera-

tions. For input operation, these ports are non-latching,

that is, the inputs must be ready at the T2 rising edge of

the

²MOV A,[m]² instruction. For output operation, all the

data is latched and remains unchanged until the output

latch is rewritten.

Each I/O line has its own control register, known as PAC

and PBC, to control the input/output configuration. With

this control register, the pin status is either a CMOS out-

put or a Schmitt trigger input, but can be reconfigured

dynamically, under software control. To function as an

input, the corresponding bit in the control register must

be written with a

²1². The input source also depends on

the control register. If the control register bit is

²1², the input

will read the pad state. If the control register bit is

²0², the

contents of the latches will move to the internal bus. The

latter is possible in the read-modify-write instruction.

When setup as an output the output types are CMOS.

After a device reset, the I/O ports will be initially all setup

as inputs, and will therefore be in a high state if the

configuration options have selected pull-high resistors,

otherwise they will be in a floating condition. Each bit of

these input/output latches can be set or cleared by the

²SET [m].i² and ²CLR [m].i² instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device.

Each line of port A and port B has a pull-high option.

Once the pull-high option is selected, the I/O line will

have a pull-high resistor connected. Otherwise, the

pull-high resistors are absent. It should be noted that a

non-pull-high I/O line operating in an input mode will be

in a floating state.

The PA0, PA1 and PA2 are pin-shared with INT0, INT1

and TMR pins, respectively. Pins PA0~PA3 and

PA4~PA7 are pin-shared with RC1~RC4 and

RC9~RC12, respectively. If configuration options select

PA0~PA7 to be RC input pins, then the corresponding

bits in the PA data register and PA control register will be

unimplemented.

It is recommended that unused or not bonded out I/O

lines should be set as output pins using software in-

struction to avoid consuming power under input floating

state.

VFD Driver

The device includes a VFD driver function to drive VFD

panel high voltage filaments and buzzer. The

microcontroller communicates serially with the VFD

driver transmitting the display data into a 24-bit shift reg-

ister within the driver. This VFD driver converts the shift

necessary voltage level shifting. The microcontroller will

only transmit data to the VFD driver, no data is transmit-

ted from the VFD driver to the microcontroller.

HT45R35V Datasheet(PDF) 23 Page - Holtek Semiconductor Inc

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