HT46F49E datasheet(22/88 Pages) HOLTEK

22 / 88 page

HT46F46E/HT46F47E/HT46F48E/HT46F49E

Rev. 1.40

July 28, 2009

EWEN/ EWDS

The

²EWEN² instruction is the Erase/Write Enable in-

struction and the

²EWDS² instruction is the Erase/Write

Disable instruction. To instigate an

²EWEN² or ²EWDS²

instruction, the CS bit should first be set high, followed

by a high start bit and then the instruction code

²00². For

the

²EWEN² instruction, a ²11² should then be transmit-

ted and for the

²EWDS² instruction a ²00² should be

transmitted. Following on from this, and depending on

whether the internal EEPROM has a 128

´8or256´8

capacity, either 5-bits or 7-bits respectively, of

²don¢t-care² data should then be transmitted to com-

plete the instruction. If the device is already in the Erase

Write Disable mode then no write or erase operations

can be executed thus protecting the internal EEPROM

data. Before any write or erase instruction is executed

²EWEN² instruction must be issued. After the

²EWEN² instruction is executed, the device will remain

in the Erase Write Enable mode until a subsequent

²EWDS² instruction is issued or until the device is pow-

ered down.

ERAL

The

²ERAL² instruction is used to erase the whole con-

tents of the EEPROM memory. After it has been exe-

cuted all the data in the EEPROM will be set to

²1².To

instigate this instruction, the CS bit should be set high,

followed by a high start bit and then the instruction code

²00². Following on from this, a ²10² should then be

transmitted, and depending on whether the internal

EEPROM has a 128

´8or256´8 capacity, this should be

followed by either 5-bits or 7-bits respectively, of

²don¢t-care² data to complete the instruction. After the

²ERAL² instruction code has been transmitted, the

EEPROM data will be erased when the CS bit is cleared

to zero. The EEPROM does this by executing an inter-

nal write-cycle. This process takes place internally using

the EEPROM

¢s own internal clock and does not require

any action from the SK clock. No further instructions can

be accepted by the EEPROM until this internal write-cy-

cle has finished. To determine when the write cycle has

ended, CS should be again brought high and the DO bit

polled. If D0 is low this indicates that the internal

write-cycle is still in progress, however the D0 bit will

change to a high value when the internal write-cycle has

C S

S K

D O

D I

S t a r t b i t

S t a n d b y

t S V

t C D S

V e r i f y

B u s y

A 6

A 1

D 0

A 0

D 7

t P R

A 5

A 4

WRITE Timing

- Except HT46F49E

C S

S K

D O

S t a n d b y

D I

t S V

t C D S

V e r i f y

B u s y

S t a r t b i t

A 7

A 1

D 0

A 0

D 7

t P R

WRITE Timing

- HT46F49E

C S

S K

S t a n d b y

D I

S t a r t b i t

E W E N = 1 1

E W D S = 0 0

X X X X X - - 5 - b i t f o r 1 2 8 ´ 8 E E P R O M

X X X X X X X - - 7 - b i t f o r 2 5 6 ´ 8 E E P R O M

EWEN/EWDS Timing

HT46F49E Datasheet(PDF) 22 Page - Holtek Semiconductor Inc

HT46F49E Datasheet(HTML) 22 Page - Holtek Semiconductor Inc

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