HT46R065V datasheet(39/72 Pages) HOLTEK

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HT46R065V

Rev. 1.00

October 20, 2009

Event Counter Mode

In this mode, a number of externally changing logic

events, occurring on the external timer TCn pin, can be

recorded by the Timer/Event Counter. To operate in this

mode, the Operating Mode Select bit pair, TnM1/TnM0,

in the Timer Control Register must be set to the correct

value as shown.

Control Register Operating Mode

Select Bits for the Event Counter Mode

Bit7 Bit6

In this mode, the external timer TCn pin, is used as the

Timer/Event Counter clock source, however it is not di-

vided by the internal prescaler. After the other bits in the

Timer Control Register have been setup, the enable bit

TnON, which is bit 4 of the Timer Control Register, can

be set high to enable the Timer/Event Counter to run. If

the Active Edge Select bit, TnEG, which is bit 3 of the

Timer Control Register, is low, the Timer/Event Counter

will increment each time the external timer pin receives

a low to high transition. If the TnEG is high, the counter

will increment each time the external timer pin receives

a high to low transition. When it is full and overflows, an

interrupt signal is generated and the Timer/Event Coun-

ter will reload the value already loaded into the preload

abled by ensuring that the Timer/Event Counter Inter-

rupt Enable bit in the corresponding Interrupt Control

As the external timer pin is shared with an I/O pin, to en-

sure that the pin is configured to operate as an event

counter input pin, two things have to happen. The first is

to ensure that the Operating Mode Select bits in the

Timer Control Register place the Timer/Event Counter

in the Event Counting Mode, the second is to ensure

that the port control register configures the pin as an in-

put. It should be noted that in the event counting mode,

even if the microcontroller is in the Sleep Mode, the

Timer/Event Counter will continue to record externally

changing logic events on the timer input TCn pin. As a

result when the timer overflows it will generate a timer

interrupt and corresponding wake-up source.

Pulse Width Capture Mode

In this mode, the Timer/Event Counter can be utilised to

measure the width of external pulses applied to the ex-

ternal timer pin. To operate in this mode, the Operating

Mode Select bit pair, TnM1/TnM0, in the Timer Control

Control Register Operating Mode

Select Bits for the Pulse Width

Capture Mode

Bit7 Bit6

In this mode the internal clock, fSYS ,fSYS/4 or the LXT, is

used as the internal clock for the 8-bit Timer/Event

Counter. However, the clock source, fSYS, for the 8-bit

timer is further divided by a prescaler, the value of which

is determined by the Prescaler Rate Select bits

TnPSC2~TnPSC0, which are bits 2~0 in the Timer Con-

trol Register. After the other bits in the Timer Control

bit 4 of the Timer Control Register, can be set high to en-

able the Timer/Event Counter, however it will not actu-

ally start counting until an active edge is received on the

external timer pin.

T i m e r + 2

E x t e r n a l E v e n t

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 3

T i m e r + 1

Event Counter Mode Timing Chart (TnEG=1)

+ 1

+ 2

+ 3

+ 4

T i m e r

E x t e r n a l T C n

P i n I n p u t

T n O N - w i t h T n E = 0

P r e s c a l e r O u t p u t

I n c r e m e n t

T i m e r C o u n t e r

P r e s c a l e r O u t p u t i s s a m p l e d a t e v e r y f a l l i n g e d g e o f T 1 .

Pulse Width Capture Mode Timing Chart (TnE=0)

HT46R065V Datasheet(PDF) 39 Page - Holtek Semiconductor Inc

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