HT49C70L datasheet(13/44 Pages) HOLTEK

13 / 44 page

HT49R70A-1/HT49C70-1/HT49C70L

Rev. 2.20

December 16, 2009

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F;bit 6 of INTC0), which is normally

caused by a timer overflow. After the interrupt is en-

abled, and the stack is not full, and the T0F bit is set, a

subroutine call to location 0CH occurs. The related inter-

rupt request flag (T0F) is reset, and the EMI bit is

cleared to disable further interrupts. The Timer/Event

Counter 1 is operated in the same manner but its related

interrupt request flag is T1F (bit 4 of INTC1) and its sub-

routine call location is 10H.

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF;bit 5 of INTC1), that is

caused by a regular time base signal. After the interrupt

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 14H occurs. The related

interrupt request flag (TBF) is reset and the EMI bit is

cleared to disable further interrupts.

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF; bit 6 of

INTC1), that is caused by a regular real time clock sig-

nal. After the interrupt is enabled, and the stack is not

full, and the RTF bit is set, a subroutine call to location

18H occurs. The related interrupt request flag (RTF) is

reset and the EMI bit is cleared to disable further inter-

rupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the

²RETI²

instruction is executed or the EMI bit and the related in-

terrupt control bit are set both to 1 (if the stack is not full).

To return from the interrupt subroutine,

²RET² or ²RETI²

may be invoked. RETI sets the EMI bit and enables an

interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

priorities in the following table apply. These can be

masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

External interrupt 0

04H

External interrupt 1

08H

Timer/Event Counter 0 overflow

0CH

Timer/Event Counter 1 overflow

10H

Time base interrupt

14H

Real time clock interrupt

18H

The Timer/Event Counter 0 interrupt request flag, T0F,

external interrupt 1 request flag (EIF1), external inter-

rupt 0 request flag (EIF0), enable Timer/Event Counter

0 interrupt bit (ET0I), enable external interrupt 1 bit

(EEI1), enable external interrupt 0 bit (EEI0), and en-

able master interrupt bit (EMI) make up of the Interrupt

Control register 0 (INTC0) which is located at 0BH in the

RAM. The real time clock interrupt request flag (RTF),

time base interrupt request flag (TBF), Timer/Event

Counter 1 interrupt request flag (T1F), enable real time

Bit No.

Label

Function

EMI

Controls the master (global) interrupt (1=enabled; 0=disabled)

EEI0

Controls the external interrupt 0 (1=enabled; 0=disabled)

EEI1

Controls the external interrupt 1 (1=enabled; 0=disabled)

ET0I

Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)

EIF0

External interrupt 0 request flag (1=active; 0=inactive)

EIF1

External interrupt 1 request flag (1=active; 0=inactive)

T0F

Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)

Unused bit, read as

²0²

INTC0 (0BH) Register

Bit No.

Label

Function

ET1I

Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)

ETBI

Controls the time base interrupt (1=enabled; 0:disabled)

ERTI

Controls the real time clock interrupt (1=enabled; 0:disabled)

Unused bit, read as

²0²

T1F

Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)

TBF

Time base request flag (1=active; 0=inactive)

RTF

Real time clock request flag (1=active; 0=inactive)

Unused bit, read as

²0²

INTC1 (1EH) Register

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