HT49C70L datasheet(21/44 Pages) HOLTEK

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HT49R70A-1/HT49C70-1/HT49C70L

Rev. 2.20

December 16, 2009

In the pulse width measurement mode with the values of

the T0ON/T1ON and T0E/T1E bits equal to 1, after the

TMR0 (TMR1) has received a transient from low to high

(or high to low if the T0E/T1E bit is

²0²), it will start counting

until the TMR0 (TMR1) returns to the original level and re-

sets the T0ON/T1ON. The measured result remains in the

timer/event counter even if the activated transient occurs

again. In other words, only 1-cycle measurement can be

made until the T0ON/T1ON is set. The cycle measure-

ment will re-function as long as it receives further transient

pulse. In this operation mode, the timer/event counter be-

gins counting not according to the logic level but to the

transient edges. In the case of counter overflows, the

counter is reloaded from the timer/event counter register

and issues an interrupt request, as in the other two modes,

i.e., event and timer modes.

To enable the counting operation, the Timer ON bit

(T0ON: bit 4 of TMR0C; T1ON: bit 4 of TMR1C) should

be set to 1. In the pulse width measurement mode, the

T0ON/T1ON is automatically cleared after the measure-

ment cycle is completed. But in the other two modes, the

T0ON/T1ON can only be reset by instructions. The

overflow of the Timer/Event Counter 0/1 is one of the

wake-up sources and can also be applied to a PFD (Pro-

grammable Frequency Divider) output at PA3 by op-

tions. Only one PFD (PFD0 or PFD1) can be applied to

PA3 by options. If PA3 is set as PFD output, there are

two types of selections; One is PFD0 as the PFD output,

the other is PFD1 as the PFD output. PFD0, PFD1 are

the timer overflow signals of the Timer/Event Counter 0,

Timer/Event Counter 1 respectively. No matter what the

operation mode is, writinga0to ET0I or ET1I disables

Bit No.

Label

Function

0~2

Unused bit, read as

²0²

T0E

Defines the TMR0 active edge of the timer/event counter:

In Event Counter Mode (T0M1,T0M0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (T0M1,T0M0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

T0ON

Enable/disable timer counting

(0=disabled; 1=enabled)

T0S

2 to 1 multiplexer control inputs which selects the timer/event counter clock source (0=RTC

outputs; 1= system clock or system clock/4)

T0M0

T0M1

Defines the operating mode (T0M1, T0M0)

01= Event count mode (External clock)

10= Timer mode (Internal clock)

11= Pulse Width measurement mode (External clock)

00= Unused

TMR0C (0EH) Register

Bit No.

Label

Function

0~2

Unused bit, read as

²0²

T1E

Defines the TMR1 active edge of the timer/event counter:

In Event Counter Mode (T1M1,T1M0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (T1M1,T1M0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

T1ON

Enable/disable timer counting

(0= disabled; 1= enabled)

T1S

2 to 1 multiplexer control inputs to select the timer/event counter clock source

(0= option clock source; 1= system clock/4)

T1M0

T1M1

Defines the operating mode (T1M1, T1M0)

01= Event count mode (External clock)

10= Timer mode (Internal clock)

11= Pulse Width measurement mode (External clock)

00= Unused

TMR1C (11H) Register

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