MPC8548CVTAQJ datasheet(36/144 Pages) FREESCALE

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC)

A timing diagram for TBI receive appears in Figure 16.

Figure 16. TBI Single-Clock Mode Receive AC Timing Diagram

8.2.6

RGMII and RTBI AC Timing Specifications

Table 33 presents the RGMII and RTBI AC timing specifications.

Table 33. RGMII and RTBI AC Timing Specifications

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)

tSKRGT

–5006

5006

Data to clock input skew (at receiver) 2

tSKRGT

1.0

—

2.8

Clock period 3

tRGT

7.2

8.0

8.8

Duty cycle for 10BASE-T and 100BASE-TX3, 4

tRGTH/tRGT

Rise time (20%–80%)

tRGTR

—

0.75

Fall time (20%–80%)

tRGTF

—

0.75

Notes:

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and

RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise

(R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is

skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between.

5. Guaranteed by characterization.

6. In rev 1.0 silicon, due to errata, tSKRGT is -650 ps (min) and 650 ps (max). Please refer to “eTSEC 10” in the device errata

document.

tTRRX

tTRRH

tTRRF

tTRRR

RX_CLK

RCG[9:0]

Valid Data

tTRRDXKH

tTRRDVKH

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