ENC424J600 datasheet(21/168 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39935C-page 19

ENC424J600/624J600

3.2

Special Function Registers

The SFRs provide the main interface between the host

controller and the on-chip Ethernet controller logic.

Writing to these registers controls the operation of the

interface, while reading the registers allows the host

controller to monitor operations.

All registers are 16 bits wide. On the SPI and 8-bit PSP

interfaces, which are inherently byte-oriented, the

registers are split into separate high and low locations

which are designated by an “H” or “L” suffix, respec-

tively. All registers are organized in little-endian format

such that the low byte is always at the lower memory

address.

Some of the available addresses are unimplemented or

marked as reserved. These locations should not be

written to. Data read from reserved locations should be

ignored. Reading from unimplemented locations will

return ‘0’. When reading and writing to registers which

contain reserved bits, any rules stated in the register

definition should be observed.

The addresses of all user-accessible registers are

provided in Tables 3-1 through 3-6. A complete bit level

listing of the SFRs is presented in Table 3-7 (page 26).

3.2.1

E REGISTERS

SFRs with names starting with “E” are the primary

control and pointer registers. They configure and con-

trol all of the (non-MAC) top-level features of the

device, as well as manipulate the pointers that define

the memory buffers. These registers can be read and

written in any order, with any length, without concern

for address alignment.

3.2.2

MAC REGISTERS

SFRs with names that start with “MA” or “MI” are

implemented in the MAC module hardware. For this

reason, their operation differs from “E” registers in two

ways.

First, MAC registers support read and write operations

only. Individual bit set and bit clear operations cannot

be performed.

Additionally, MAC registers must always be written as

a 16-bit word, regardless of the I/O interface being

used. That is, on the SPI or 8-bit PSP interfaces, all

write operations must be performed by writing to the

low byte, followed by a write to the associated high

byte. On 16-bit PSP interfaces, both write enables or

byte selects must be asserted to perform the 16-bit

write. Non-sequential writes, such as writing to the low

byte of one MAC register, the low byte of a second

MAC register and then the high byte of the first register

cannot be performed.

3.2.3

SPI REGISTER MAP

As previously described, the SFR memory is

partitioned into four banks plus a special region that is

not bank addressable. Each bank is 32 bytes long and

addressed by a 5-bit address value. All SFR memory

may also be accessed via unbanked SPI opcodes

which use a full 8-bit address to form a linear address

map without banking.

The last 10 bytes (16h to 1Fh) of all SPI banks point to

a common set of five registers: EUDAST, EUDAND,

ESTAT, EIR and ECON1. These are key registers used

in controlling and monitoring the operation of the

device. Their common banked addresses allow easy

access without switching the bank.

The SPI interface implements a comprehensive

instruction set that allows for reading and writing of

registers, as well as setting and clearing individual bits

or bit fields within registers. The SPI instruction set is

explained in detail in Section 4.0 “Serial Peripheral

Interface (SPI)”.

The SFR map for the SPI interface is shown in

Table 3-1. Registers are presented by a bank. The

banked (5-bit) address applicable to the registers in

each row is shown in the left most column. The

unbanked (8-bit) address for each register is shown to

the immediate left of the register name.

Note:

SFRs in the unbanked region (80h through

9Fh) cannot be accessed using banked

addressing. The use of an unbanked SFR

opcode is required to perform operations

on these registers.

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