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AS8520

Preliminary Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

8.7 Serial Port Interface

The 4-wire interface is essentially used to control the relay driver, to shutdown LDO temporarily and to trigger the window watchdog. It is also

used to access test mode and read out diagnostic information for the AS8520. The description of this interface and the protocol is explained

below. Information on block status and errors can be displayed by diagnosis registers.

8.7.1 Device Configuration using 4-Wire Serial Port

The SPI interface can be used as interface between the AS8520 and an external microcontroller to configure the device and access the status

information. The interface is a slave and then only the microcontroller can start the communication. The SPI protocol is very simple and the

length of each frame is an integer multiple of byte except when a transmission is started. Basically each frame has 1 command bit, 5 address/

configuration bits, 1 or more data bytes. SPI clock polarity settings depend on the value of the SCLK on the CS falling edge. This setting is done

on each start of the SPI transaction. During the transaction, the SPI clock polarity will be fixed to the settings done. On the CS falling edge, the

values on SCLK signal decide setting of the active SPI clock edge for data transfer. (see table below)

8.7.1.1 SPI Frame

A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of

bytes. Command is coded on the 1 first bit, while address is given on LSB 5 bits. (see table below)

If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling),

the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.

8.7.1.2 Write Command

For Write command C0 = 0.

After the command code C0 and two reserved bits, the address of register to be written has to be provided from the MSB to the LSB. Then one

or more data bytes can be transferred, always from the MSB to the LSB. For each data byte following the first one, used address is the

incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge and

the SPI slave on the next SPI clock edge samples it. These edges are selected as per Table 17. The following figures illustrate two examples of

write command (without and with address self-increment.)

Table 17. CS and SCLK

CS

SCLK

Description

FALL

LOW

Serial data transferred on rising edge of SPI clock. Sampled at falling

edge of SPI clock.

FALL

HIGH

Serial data transferred on falling edge of SPI clock. Sampled at rising

edge of SPI clock.

ANY

ANY

Serial data transfer edge is unchanged.

Table 18. Command Bits

Command Bits

Register Address or Transmission Configuration

C0

Reserved

Reserved

A4

A3

A2

A1

A0

C0

Command

<A4:A0>

Description

0

WRITE

ADDRESS

Writes data byte on the given starting address.

1

READ

ADDRESS

Read data byte from the given starting address.