DSPIC33FJ32GS608 datasheet(200/416 Pages) MICROCHIP

200 / 416 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591B-page 200

Preliminary

 2009 Microchip Technology Inc.

10.2.2

IDLE MODE

The following occur in Idle mode:

• The CPU stops executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 10.5

“Peripheral Module Disable”).

• If the WDT or FSCM is enabled, the LPRC also

remains active.

The device will wake-up from Idle mode on any of these

events:

• Any interrupt that is individually enabled

• Any device Reset

• A WDT time-out

On wake-up from Idle mode, the clock is reapplied to

the CPU and instruction execution will begin (2-4 clock

cycles later), starting with the instruction following the

PWRSAV instruction, or the first instruction in the ISR.

10.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAV instruction is held off until entry into Sleep or

Idle mode has completed. The device then wakes up

from Sleep or Idle mode.

10.3

Doze Mode

The

preferred

strategies

for

reducing

power

consumption are changing clock speed and invoking

one

the

power-saving

modes.

some

circumstances, this may not be practical. For example,

it may be necessary for an application to maintain

uninterrupted synchronous communication, even while

it is doing nothing else. Reducing system clock speed

can introduce communication errors, while using a

power-saving

mode

can

stop

communications

completely.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock

continues to operate from the same source and at the

same speed. Peripheral modules continue to be

clocked at the same speed, while the CPU clock speed

is reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>).

There

are

eight

possible

configurations, from 1:1 to 1:128, with 1:1 being the

default setting.

Programs can use Doze mode to selectively reduce

power consumption in event-driven applications. This

allows clock-sensitive functions, such as synchronous

communications, to continue without interruption while

the CPU idles, waiting for something to invoke an

interrupt routine. An automatic return to full-speed CPU

operation on interrupts can be enabled by setting the

ROI bit (CLKDIV<15>). By default, interrupt events

have no effect on Doze mode operation.

For example, suppose the device is operating at

20 MIPS and the CAN module has been configured for

500 kbps based on this device operating speed. If the

device is placed in Doze mode with a clock frequency

ratio of 1:4, the CAN module continues to communicate

at the required bit rate of 500 kbps, but the CPU now

starts executing instructions at a frequency of 5 MIPS.

10.4

PWM Power-Saving Features

Typically, many applications need either a high

resolution duty cycle or phase offset (for fixed

frequency operation) or a high resolution PWM period

for variable frequency modes of operation (such as

Resonant mode). Very few applications require both

high resolution modes simultaneously.

The HRPDIS and the HRDDIS bits in the AUXCONx

registers permit the user to disable the circuitry associ-

ated with the high resolution duty cycle and PWM

period to reduce the operating current of the device.

If the HRDDIS bit is set, the circuitry associated with

the high resolution duty cycle, phase offset, and dead

time for the respective PWM generator is disabled. If

the HRPDIS bit is set, the circuitry associated with the

high resolution PWM period for the respective PWM

generator is disabled.

When the HRPDIS bit is set, the smallest unit of

measure for the PWM period is 8.32 ns.

If the HRDDIS bit is set, the smallest unit of measure

for the PWM duty cycle, phase offset and dead time is

8.32 ns.

dsPIC33FJ32GS608 Datasheet(PDF) 200 Page - Microchip Technology

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