DSPIC33FJ32GS608 datasheet(201/416 Pages) MICROCHIP

201 / 416 page

 2009 Microchip Technology Inc.

Preliminary

DS70591B-page 201

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

10.5

Peripheral Module Disable

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled using the appropriate

PMD control bit, the peripheral is in a minimum power

consumption state. The control and STATUS registers

associated with the peripheral are also disabled, so

writes to those registers will have no effect and read

values will be invalid.

A peripheral module is enabled only if both the

associated bit in the PMD register is cleared and the

peripheral is supported by the specific dsPIC® DSC

variant. If the peripheral is present in the device, it is

enabled in the PMD register by default.

Note:

If a PMD bit is set, the corresponding

module is disabled after a delay of one

instruction cycle. Similarly, if a PMD bit is

cleared, the corresponding module is

enabled after a delay of one instruction

cycle (assuming the module control regis-

ters are already configured to enable

module operation).

dsPIC33FJ32GS608 Datasheet(PDF) 201 Page - Microchip Technology