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VG3617161DT Datasheet(PDF) 21 Page - Vanguard International Semiconductor |
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VG3617161DT Datasheet(HTML) 21 Page - Vanguard International Semiconductor |
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21 / 70 page  Document:1G5-0160 Rev.1 Page 21 VIS Preliminary VG3617161DT 16Mb CMOS Synchronous Dynamic RAM 8.2 WRITE with AUTO PRECHARGE During a WRITA cycle, the AUTO PRECHARGE starts at tDPL(min.) after the last data word input to the device WRITE with AUTO PRECHRGE In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference. CAS latency READ WRITE 2 -1 +tDPL(min.) 3 -2 +tDPL(min) Burst lengh=4 CLK Command CAS latency=2 DQ Command CAS latency=3 DQ Remark WRITA means WRITE with AUTO PRECHARGE Hi-Z DB0 DB3 DB2 DB1 WRITA B WRITA B T0 T1 T2 T3 T4 T5 T6 T7 Hi-Z_ T8 tDPL tDPL DB0 DB3 DB2 DB1 AUTO PRECHARGE starts AUTO PRECHARGE starts |
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