VG3617161DT datasheet(7/70 Pages) VML

7 / 70 page

Document:1G5-0160

Rev.1

Page 7

VIS

Preliminary

VG3617161DT

16Mb CMOS Synchronous Dynamic RAM

Note:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

2. All voltages are referenced to VSS.

3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK

and tRC. Input signals are changed one time during tCK. Assume that there are only one read/write cycle during tRC (min).

4. These parameters depend on the output loading. Specified values are obtained with the output open.

5. Assume minimum column address update cycle tCCD (min).

6. Power-up sequence is described in Note 10.

7. A.C. Test Conditions

8. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are fixed slope (1 ns).

9. tHZ defines the time at which the outputs achieve the open circuit condition and are not reference levels.

10. Power up Sequence

Power up must be performed in the following sequence.

1) Power must be applied to VDD and VDDQ (simultaneously) when all input signals are held “NOP” state and

CKE = ”H”, DQM = ”H”. The CLK signals must be started at the same time.

2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that DQM is held

“high” (V DD levels) to ensure DQ output to be in the high impedance.

3) Both banks must be precharged.

4) Mode Register Set command must be asserted to initialize the Mode register.

Reference Level of Output Signals

1.4V / 1.4V

Output Load

Reference to the Under Output Load (B)

Input Signal Levels

3.0V / 0.0V

Transition Time (Rise and Fall) of Input Signals

1ns

Reference Level of Input Signals

1.4V

3.3V

1.2K

870

30pF

Output

LVTTL D.C. Test Load (A)

1.4V

30pF

Output

ZO=50

LVTTL A.C. Test Load (B)

Ω

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