VG3617801CT datasheet(13/68 Pages) VML

13 / 68 page

Document:1G5-0133

Rev.1

Page 13

VIS

VG3617801CT

16Mb CMOS Synchronous Dynamic RAM

3.Initiallization

The synchronous DRAM is initialized in the power on sequence. Once power has been applied, a

100us minimum delay is needed in which stable power and input signals are maintained. During this delay,

CKE and DQM recommend to be held high.

After the 100us delay, both banks must be precharged using the precharge command. Once precharge

is completed and the minimum tRP is satisfied, the mode register can be programmed.

Minimum two CBR refresh commands must be performed before or after the mode register set com-

mand.

4.Programming the Mode Register

The mode register is programmed by the mode register set command using address bits A11 through

A0 as data inputs. The register retains data until it is reprogrammed or until the device loses power.

The mode register has four fields;

Options

: A11 through A7

CAS latency

: A6 through A4

Wrap type

: A3

Burst length

: A2 through A0

Following mode register programming, no command can be asserted befor at least two clock cycles

have elapsed.

CAS Latency

CAS latency is the most critical parameter to be set. It tells the device how many clocks must elapse

before the data will be available. The SDRAM is capable of reconfiguring its internal architecture based

on the value of CAS latency.

The value is determined by the frequency of the clock and the speed grade of the device. The value

can be programmed as 2 or 3.

Burst Length

Burst Length is the number of words that will be output or input in read or write cycle. After a read burst

is completed, the output bus will become high impedance.

The burst length is programmable as 1,2,4,8 or full page.

Wrap Type (Burst Sequence)

The wrap type specifies the order in which the burst data will be addressed. The order is programmable

as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.

Some microprocessor cache systems are optimized for sequential addressing and others for inter-

leaved addressing. Both sequences support bursts of 1,2,4 and 8. Only the sequential burst. supports the

full-page length.

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