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VG36648041CT Datasheet(PDF) 21 Page - Vanguard International Semiconductor |
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VG36648041CT Datasheet(HTML) 21 Page - Vanguard International Semiconductor |
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21 / 70 page  Document : 1G5-0153 Rev.1 Page 21 VIS Preliminary VG36648041CT CMOS Synchronous Dynamic RAM 8.4 Multibank Operation- Write with Auto Precharge During a WRITEA cycle interrupted by a Read, Write command of another banks, the auto-pre- charge scheduled time would not be changed. CLK Command CAS latency=2 DQ Command CAS latency=3 DQ Hi-Z T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Burst lengh=8 Auto precharge bank A starts WRITA A Read B DA0 DA1 DB0 DB1 DB2 DB3 DB4 DB5 Hi-Z Auto precharge bank A starts WRITA A Read B DA0 DA1 DB0 DB1 DB2 DB3 DB4 CLK Command CAS latency=2 DQ Command CAS latency=3 DQ Hi-Z T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Burst lengh=8 Auto precharge bank A starts WRITA A Write B DA0 DA1 DB0 DB1 DB2 DB3 DB4 DB6 DB7 Hi-Z Auto precharge bank A starts WRITA A Write B DA0 DA1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB5 Multibank Operation Multibank Operation |
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