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VG36648041CT Datasheet(PDF) 7 Page - Vanguard International Semiconductor

Part # VG36648041CT
Description  CMOS Synchronous Dynamic RAM
PDF  70 Pages
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Manufacturer  VML [Vanguard International Semiconductor]
Direct Link  http://www.vis.com.tw
Logo VML - Vanguard International Semiconductor

VG36648041CT Datasheet(HTML) 7 Page - Vanguard International Semiconductor

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Document : 1G5-0153
Rev.1
Page 7
VIS
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
Parameter
CAS
Latency
symbol
VG36648041B
Unit
-7
-8
Min
Max
Min
Max
CLK cycle time
3
tck3
7
8
ns
2
tck2
10
10
ns
CLK to valid output delay
3
tAc3
6
6
ns
2
tAc2
6
6
ns
CLK high pulse width
tCH
3
3
ns
CLK low pulse width
tCL
3
3
ns
CKE setup time
tCKS
2
2
ns
CKE hold time
tCKH
1
1
ns
Address setup time
tAS
2
2
ns
Address hold time
tAH
1
1
ns
Command setup time
tCMS
2
2
ns
Command hold time
tCMH
1
1
ns
Data input setup time
tDS
2
2
ns
Data input hold time
tDH
1
1
ns
Output data hold time
tOH
3
3
ns
CLK to output in low - Z
tLZ
0
0
ns
CLK to output in H - Z
3
tHZ
5
6
ns
2
6
6
Row active to active delay
tRRD
14
16
ns
RAS to CAS delay
tRCD
20
20
ns
Row precharge time
tRP
20
20
ns
ROW active time
tRAS
40
120K
48
120K
ns
ROW cycle time
tRC
60
68
ns
Last data in to burst stop
tBDL
1
1
CLK
Data - in to ACT(REF) command
tDAL
1+ tRP
1+tRP
CLK
Data - in to precharge
tDPL
1
1
CLK
Transition time
tT
1
10
1
10
ns
Mode reg. set cycle
tRSC
2
2
CLK
Power down exit setup time
tPDE
2
2
ns
Self refresh exit time
tSRX
1
1
CLK
Refresh time
tREF
64
64
ms
A. C Characteristics : (Ta = 0 to 70°C VDD = 3.3V 0.3V, VSS = 0V)



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