Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

WM8728 Datasheet(PDF) 6 Page - Wolfson Microelectronics plc

Part # WM8728
Description  24-bit, 192kHz Stereo DAC with Volume Control and DSD Support
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8728 Datasheet(HTML) 6 Page - Wolfson Microelectronics plc

Back Button WM8728 Datasheet HTML 2Page - Wolfson Microelectronics plc WM8728 Datasheet HTML 3Page - Wolfson Microelectronics plc WM8728 Datasheet HTML 4Page - Wolfson Microelectronics plc WM8728 Datasheet HTML 5Page - Wolfson Microelectronics plc WM8728 Datasheet HTML 6Page - Wolfson Microelectronics plc WM8728 Datasheet HTML 7Page - Wolfson Microelectronics plc WM8728 Datasheet HTML 8Page - Wolfson Microelectronics plc WM8728 Datasheet HTML 9Page - Wolfson Microelectronics plc WM8728 Datasheet HTML 10Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 28 page
background image
WM8728
Product Preview
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
6
MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25
oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Master Clock Timing Information
MCLK Master clock pulse width high
tMCLKH
13
ns
MCLK Master clock pulse width low
tMCLKL
13
ns
MCLK Master clock cycle time
tMCLKY
26
ns
MCLK Duty cycle
40:60
60:40
DIGITAL AUDIO INTERFACE
BCKIN
LRCIN
t
BCH
t
BCL
t
BCY
DIN
t
LRSU
t
DS
t
LRH
t
DH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25
oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
40
ns
BCKIN pulse width high
tBCH
16
ns
BCKIN pulse width low
tBCL
16
ns
LRCIN set-up time to
BCKIN rising edge
tLRSU
8ns
LRCIN hold time from
BCKIN rising edge
tLRH
8ns
DIN set-up time to BCKIN
rising edge
tDS
8ns
DIN hold time from BCKIN
rising edge
tDH
8ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com