WM8728

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WOLFSON MICROELECTRONICS LTD

PP Rev 1.2 April 2001

10

MPU 2-WIRE INTERFACE TIMING

SCKDSD

SDIDEM

t

t

SCY

t

SCH

t

SCL

t

DSU

t

DHD

t

SCR

t

SCF

t

DF

t

DR

t

ESU

Figure 6 Program Register Input Timing - 2-Wire Serial Control Mode

Test Conditions

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Program Register Input Information

SCKDSD pulse cycle time

80

ns

SCKDSD pulse width low

20

ns

SCKDSD pulse width high

20

ns

SDIDEM to SCKDSD data set-

up time for start signal

10

ns

SDIDEM from SCKDSD data

hold time for start signal

10

ns

SDIDEM to SCKDSD data set-

up time

20

ns

SCKDSD to SDIDEM data hold

time

20

ns

SCKDSD rise time

5ns

SCKDSD fall time

5ns

SDIDEM rise time

5ns

SDIDEM fall time

5ns

SDIDEM to SCKDSD data set-

up time for stop signal

10

ns

Notes:

1.

The address for the device in the 2-wire mode is 001101X (binary) with the last bit selectable.

2.

In the two-wire interface mode, the CSBIWL pin indicates the final bit of the chip address.

3.

In 2-wire mode the LATI2S pin should be tied to either DGND or DVSS to avoid noise toggling the interface into 3-wire

mode.