AD9553SLASHPCBZ datasheet(39/44 Pages) AD

39 / 44 page

AD9553

Rev. 0 | Page 39 of 44

OUT1 Driver Control (Register 0x32)

Table 37.

Address

Bit

Bit Name

Description

0x32

OUT1 drive strength

Controls the output drive capability of the OUT1 driver.

0 = weak.

1 = strong (default).

OUT1 power-down

Controls power-down functionality of the OUT1 driver.

0 = OUT1 active (default).

1 = OUT1 powered down.

[5:3]

OUT1 mode control

OUT1 driver mode selection.

000 = CMOS, both pins active.

001 = CMOS, positive pin active, negative pin tristate.

010 = CMOS, positive pin tristate, negative pin active.

011 = CMOS, both pins tristate.

100 = LVDS.

101 = LVPECL (default).

110 = not used.

111 = not used.

[2:1]

OUT1 CMOS polarity

Selects the polarity of the OUT1 pins in CMOS mode.

00 = positive pin is normal polarity and negative pin is inverted polarity (default).

01 = positive pin is normal polarity and negative pin is normal polarity.

10 = positive pin is inverted polarity and negative pin logic is inverted polarity.

11 = positive pin logic is inverted polarity and negative pin is normal polarity.

These bits are ineffective unless Bits[5:3] select CMOS mode. See the Output Driver

Polarity (CMOS) section for the definition of normal and inverted polarity.

Use Bits[5:3] as source for

OUT1 mode control

Controls OUT1 driver functionality.

0 = OUT1 mode determined by the OM[2:0] pins (default).

1 = OUT1 mode defined by Register 0x32[5:3].

Reserved (Register 0x33)

Table 38.

Address

Bit

Bit Name

Description

0x33

[7:0]

Unused

Unused.

AD9553/PCBZ Datasheet(PDF) 39 Page - Analog Devices

AD9553/PCBZ Datasheet(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL