AD9553SLASHPCBZ datasheet(22/44 Pages) AD

22 / 44 page

AD9553

Rev. 0 | Page 22 of 44

Loop Filter

The charge pump in the PFD delivers current to the loop filter

(see Figure 22). The main components of the loop filter are

external and connect between Pin 16 and Pin 17. Note that to

achieve the best jitter performance in applications requiring a loop

bandwidth of less than 1 kHz, C1 and C2 must have an insulation

resistance of at least 500 ΩF.

Ω

FROM

CHARGE

PUMP

VCO

5pF

AD9553

FILTER

LDO

EXTERNAL LOOP FILTER

COMPONENTS

Figure 22. External Loop Filter

There are two recommended sets of external loop filter com-

ponents (see Table 17) based on the A[3:0] pin configuration.

Table 17. External Loop Filter Components

Pins A[3:0]

R (kΩ) C1

Loop Bandwidth (kHz)

0001 to

1100

6.8

47 nF

1 μF

0.17

1101 to

1110

51 pF

220 nF

1111

6.8

47 nF

1 μF

0.17

PLL Locked Indicator

The PLL provides a status indicator that appears at Pin 20

(LOCKED). When the PLL acquires phase lock, the LOCKED

pin switches to a Logic 1 state.

Alternatively, the LOCKED pin serves as a test port allowing the

user to monitor one-of-four internal clocks. Register 0x17[3:1]

controls the test port as shown in Table 18.

Table 18: LOCKED Pin Output Control

0x17[3:1]

LOCKED Pin Output

0XX

PLL locked indication (default)

100

Crystal oscillator clock signal

101

PFD pump-up clock divided-by-2

110

PFD reference input clock divided-by-2

111

PLL feedback to PFD clock divided-by-2

Output Dividers

The output divider section consists of three dividers: P0, P1, and P2.

The P0 divider (or VCO frequency prescaler) accepts the VCO

frequency and reduces it by a factor of 5 or 6 (selectable). This

brings the frequency down to a range between 558 MHz and

810 MHz.

The output of the P0 divider independently drives the P1 divider

and the P2 divider. The P1 divider establishes the frequency at

OUT1 and the P2 divider establishes the frequency at OUT2.

The P1 and P2 dividers are each programmable over a range of

1 to 1023, which results in a frequency at OUT1 or OUT2 that

is an integer submultiple of the frequency at the output of the P0

divider.

Output Driver Configuration

The user has complete control over all configurable parameters

of the OUT1 and OUT2 drivers via the OUT1 and OUT2 driver

control registers (Register 0x32 and Register 0x34, respectively,

as shown in Figure 23). To alter the parameters from their

default values, the user must use the SPI port to program the

driver control registers as desired.

The OUT1 and OUT2 drivers are configurable in terms of the

following parameters:

•

Logic family (via mode control)

•

Pin function (via mode control but only applies to the

CMOS family)

•

Polarity (only applies to the CMOS family)

•

Drive current

•

Power-down

Output Driver Mode Control

Three mode control bits establish the logic family and pin

function of the output drivers. The three bits originate either

from Bits[5:3] of Register 0x32 and Register 0x34 or from the

decode logic associated with the OM[2:0] pins as shown in

Figure 23. Note that Bit 0 of Register 0x32 and Register 0x34

determines the source of the three mode control bits for the

associated output driver. Specifically, when Bit 0 of the register

is Logic 0 (default), the source of the mode control bits for the

associated driver is the OM[2:0] pin decoder. When Bit 0 is

Logic 1, the source of the mode control bits is from Bits[5:3] of

The mode control bits establish the logic family and output pin

function of the associated output driver per Table 19. The logic

families include LVDS, LVPECL, and CMOS. Because both

output drivers support the LVDS and LVPECL logic families,

each driver has two pins to handle the differential signals

associated with these two logic families. The OUT1 driver uses

the OUT1 and OUT1 pins and the OUT2 driver uses the OUT2

and OUT2 pins. However, the CMOS logic family handles only

single-ended signals, thereby requiring only one pin. Even

though CMOS only requires one pin, both pins of OUT1 and

both pins of OUT2 have a dedicated CMOS driver.

The user has the option to disable (that is, tristate) either or

both of the pins for OUT1 and/or OUT2 via the mode control

bits (see Table 19, Bit Patterns 001, 010, and 011). Alternatively,

the user can make both pins active (see Table 19, Bit Pattern

000) to produce two single-ended CMOS output clocks at

OUT1 and/or OUT2.

AD9553/PCBZ Datasheet(PDF) 22 Page - Analog Devices

AD9553/PCBZ Datasheet(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL