LPC2194 datasheet(21/40 Pages) NXP

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LPC2194_5

Product data sheet

Rev. 05 — 10 December 2007

21 of 40

NXP Semiconductors

LPC2194

Single-chip 16/32-bit microcontroller

Remark: Devices without the /00 or /01 sufﬁxes have only a security level equivalent to

CRP2 available.

6.18.5 External interrupt inputs

The LPC2194 include up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The External Interrupt Inputs can optionally be used

to wake-up the processor from Power-down mode.

6.18.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip SRAM. This allows code running in different memory

spaces to have control of the interrupts.

6.18.7 Power control

The LPC2194 support two reduced power modes: Idle mode and Power-down mode. In

Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a Reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.18.8 APB

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB so that they can operate at the

speed chosen for the ARM processor. In order to achieve this, the APB may be slowed

down to 1

⁄

2 to

⁄

4 of the processor clock rate. Because the APB must work properly at

power-up (and its timing cannot be altered if it does not work since the APB divider control

registers reside on the APB), the default condition at reset is for the APB to run at 1

⁄

4 of the

processor clock rate. The second purpose of the APB divider is to allow power savings

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

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