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P89LPC9211FDH Datasheet(PDF) 64 Page - NXP Semiconductors |
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P89LPC9211FDH Datasheet(HTML) 64 Page - NXP Semiconductors |
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64 / 74 page ![]() P89LPC92X1_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 16 April 2009 64 of 74 NXP Semiconductors P89LPC9201/9211/922A1/9241/9251 8-bit microcontroller with 8-bit ADC 11.1 Waveforms 11.2 ISP entry mode Fig 32. Shift register mode timing 01 2 3 4 5 6 7 valid valid valid valid valid valid valid valid TXLXL 002aaa906 set TI set RI tXHQX tQVXH tXHDV tXHDX clock output data write to SBUF input data clear RI Fig 33. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 Table 16. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tVR VDD active to RST active delay time pin RST 50 - - µs tRH RST HIGH time pin RST 1 - 32 µs tRL RST LOW time pin RST 1 - - µs Fig 34. ISP entry waveform 002aaa912 VDD RST tRL tVR tRH |
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