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[1]

All ports are in input only (high impedance) state after power-up.

[2]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any of them is written if BRGEN = 1, result is unpredictable.

[3]

The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

xx11 0000.

[4]

After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

The only reset source that affects these SFRs is power-on reset.

WDL

Watchdog load

C1H

FF

1111 1111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 9.

* indicates SFRs that are bit addressable.

Name

Description

SFR

addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary