P89LPC9402 datasheet(21/60 Pages) NXP

21 / 60 page

P89LPC9402_1

Product data sheet

Rev. 01 — 22 April 2009

21 of 60

NXP Semiconductors

P89LPC9402

8-bit microcontroller with accelerated two-clock 80C51 core

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC9402 has 8 kB of on-chip Code memory.

7.12 Data RAM arrangement

The 768 bytes of on-chip RAM are organized as shown in Table 6.

7.13 Interrupts

The P89LPC9402 uses a four priority level interrupt structure. This allows great ﬂexibility

in controlling the handling of the many interrupt sources. The P89LPC9402 supports

13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port

RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard,

comparators 1 and 2, SPI.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global

disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt, but

not by another interrupt of the same or lower priority. The highest priority interrupt service

cannot be interrupted by any other interrupt source. If two requests of different priority

levels are pending at the start of an instruction, the request of higher priority level is

serviced.

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

7.13.1 External interrupt inputs

The P89LPC9402 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard 80C51

microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an

interrupt request.

If an external interrupt is enabled when the P89LPC9402 is put into Power-down or Idle

mode, the interrupt will cause the processor to wake-up and resume operation. Refer to

Section 7.16 “Power reduction modes” for details.

Table 6.

On-chip data memory usages

Type

Data RAM

Size (bytes)

DATA

Memory that can be addressed directly and indirectly

128

IDATA

Memory that can be addressed indirectly

256

P89LPC9402 Datasheet(PDF) 21 Page - NXP Semiconductors

P89LPC9402 Datasheet(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL