P89LPC9402 datasheet(39/60 Pages) NXP

39 / 60 page

P89LPC9402_1

Product data sheet

Rev. 01 — 22 April 2009

39 of 60

NXP Semiconductors

P89LPC9402

8-bit microcontroller with accelerated two-clock 80C51 core

7.27.5 Timing

The LCD controller timing controls the internal data ﬂow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. The timing

also generates the LCD frame signal whose frequency is derived from the clock

frequency. The frame signal frequency is a ﬁxed division of the clock frequency from either

the internal or an external clock.

Frame frequency = fosc(LCD)/24.

7.27.6 Display register

A display latch holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display latch, the

LCD segment outputs, and each column of the display RAM.

7.27.7 Segment outputs

The LCD drive section includes 32 segment outputs S0 to S31. The segment output

signals are generated according to the multiplexed backplane signals and the display

latch data. When less than 32 segment outputs are required, the unused segment outputs

should be left open-circuit.

7.27.8 Backplane outputs

The LCD drive section has four backplane outputs BP0 to BP3. The backplane output

signals are generated in based on the selected LCD drive mode. If less than four

backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3

multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent

outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive

mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be

paired to increase the drive capabilities. In the static drive mode the same signal is carried

by all four backplane outputs and they can be connected in parallel for very high drive

requirements.

7.27.9 Display RAM

The display RAM is a static 32

× 4-bit RAM which stores LCD data. There is a one-to-one

correspondence between the RAM addresses and the segment outputs, and between the

individual bits of a RAM word and the backplane outputs. The ﬁrst RAM column

corresponds to the 32 segments for backplane 0 (BP0). In multiplexed LCD applications

the segment data of the second, third and fourth column of the display RAM are

time-multiplexed with BP1, BP2 and BP3 respectively.

7.27.10 Data pointer

The Display RAM is addressed using the data pointer. Either a single byte or a series of

display bytes may be loaded into any location of the display RAM.

7.27.11 Output bank selector

The LCD controller includes a RAM bank switching feature in the static and 1:2 drive

modes. In the static drive mode, the BANK SELECT command may request the contents

of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the contents

of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to

be prepared in an alternative bank and then selected for display when it is assembled.

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