PIC16F707-ESLASHP datasheet(51/284 Pages) MICROCHIP

51 / 284 page

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 51

PIC16F707/PIC16LF707

6.0

I/O PORTS

There are thirty-five general purpose I/O pins available.

Depending on which peripherals are enabled, some or

all of the pins may not be available as general purpose

I/O. In general, when a peripheral is enabled, the

associated pin may not be used as a general purpose

I/O pin.

Each port has two registers for its operation. These

registers are:

• TRISx registers (data direction register)

• PORTx registers (port read/write register)

Ports with analog functions also have an ANSELx

power. A simplified model of a generic I/O port, without

the interfaces to other peripherals, is shown in

Figure 6-1.

FIGURE 6-1:

GENERIC I/O PORT

OPERATION

6.1

Alternate Pin Function

The Alternate Pin Function Control (APFCON) register

is used to steer specific peripheral input and output

functions between different pins. The APFCON register

is shown in Register 6-1. For this device family, the

following functions can be moved between different

pins.

•SS (Slave Select)

• CCP2

Data Register

I/O pin

Read PORTx

Write PORTx

TRISx

Data Bus

To peripherals

ANSELx

VDD

VSS

APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

U-0

R/W-0

—

SSSEL

CCP2SEL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-2

Unimplemented: Read as ‘0’.

bit 1

SSSEL: SS Input Pin Selection bit

0 =SS function is on RA5/AN4/CPS7/SS/VCAP

1 =SS function is on RA0/AN0/SS/VCAP

bit 0

CCP2SEL: CCP2 Input/Output Pin Selection bit

0 = CCP2 function is on RC1/T1OSI/CCP2

1 = CCP2 function is on RB3/CCP2

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