PIC18F23K20-ESLASHML datasheet(266/456 Pages) MICROCHIP

266 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 266

 2010 Microchip Technology Inc.

19.1

ADC Configuration

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Results formatting

19.1.1

PORT CONFIGURATION

The ANSEL, ANSELH, TRISA, TRISB and TRISE reg-

isters all configure the A/D port pins. Any port pin

needed as an analog input should have its correspond-

ing ANSx bit set to disable the digital input buffer and

TRISx bit set to disable the digital output driver. If the

TRISx bit is cleared, the digital output level (VOH or

VOL) will be converted.

The A/D operation is independent of the state of the

ANSx bits and the TRIS bits.

19.1.2

CHANNEL SELECTION

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 19.2

“ADC Operation” for more information.

19.1.3

ADC VOLTAGE REFERENCE

The VCFG bits of the ADCON1 register provide

independent control of the positive and negative

voltage references. The positive voltage reference can

be either VDD or an external voltage source. Likewise,

the negative voltage reference can be either VSS or an

external voltage source.

19.1.4

SELECTING AND CONFIGURING

ACQUISITION TIME

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set.

Acquisition time is set with the ACQT<2:0> bits of the

ADCON2 register. Acquisition delays cover a range of

2 to 20 TAD. When the GO/DONE bit is set, the A/D

module continues to sample the input for the selected

acquisition time, then automatically begins a conver-

sion. Since the acquisition time is programmed, there is

no need to wait for an acquisition time between select-

ing a channel and setting the GO/DONE bit.

Manual

acquisition

selected

when

ACQT<2:0> = 000. When the GO/DONE bit is set,

sampling is stopped and a conversion begins. The user

is responsible for ensuring the required acquisition time

has passed between selecting the desired input

channel and setting the GO/DONE bit. This option is

also the default Reset state of the ACQT<2:0> bits and

compatible

with

devices

that

not

offer

programmable acquisition times.

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set and the

A/D begins sampling the currently selected channel

again. When an acquisition time is programmed, there

is no indication of when the acquisition time ends and

the conversion begins.

19.1.5

CONVERSION CLOCK

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON2 register. There

are seven possible clock options:

•FOSC/2

•FOSC/4

•FOSC/8

•FOSC/16

•FOSC/32

•FOSC/64

•FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11 TAD periods

as shown in Figure 19-3.

For correct conversion, the appropriate TAD specification

must be met. See A/D conversion requirements in

Table 26-25 for more information. Table 19-1 gives

examples of appropriate ADC clock selections.

Note 1: When reading the PORT register, all pins

with their corresponding ANSx bit set

read as cleared (a low level). However,

analog conversion of pins configured as

digital inputs (ANSx bit cleared and

TRISx

bit

set)

will

accurately

converted.

2: Analog levels on any pin with the corre-

sponding ANSx bit cleared may cause the

digital input buffer to consume current out

of the device’s specification limits.

3: The

PBADEN

bit

Configuration

reset as analog or digital pins by

controlling how the bits in ANSELH are

reset.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC

clock

frequency,

which

may

adversely affect the ADC result.

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