PIC18F23K20-ESLASHML datasheet(269/456 Pages) MICROCHIP

269 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 269

PIC18F2XK20/4XK20

19.2.2

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF flag bit

• Update the ADRESH:ADRESL registers with new

conversion result

19.2.3

DISCHARGE

The discharge phase is used to initialize the value of

the capacitor array. The array is discharged after every

sample. This feature helps to optimize the unity-gain

amplifier, as the circuit always needs to charge the

capacitor array, rather than charge/discharge based on

previous measure values.

19.2.4

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared by software. The

ADRESH:ADRESL registers will not be updated with

the partially complete Analog-to-Digital conversion

sample. Instead, the ADRESH:ADRESL register pair

will retain the value of the previous conversion.

19.2.5

DELAY BETWEEN CONVERSIONS

After the A/D conversion is completed or aborted, a

2TAD wait is required before the next acquisition can

be started. After this wait, the currently selected

channel is reconnected to the charge holding capacitor

commencing the next acquisition.

19.2.6

ADC OPERATION IN POWER-

MANAGED MODES

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

power-managed

mode,

the

ACQT<2:0>

and

ADCS<2:0> bits in ADCON2 should be updated in

accordance with the clock source to be used in that

mode. After entering the mode, an A/D acquisition or

conversion may be started. Once started, the device

should continue to be clocked by the same clock

source until the conversion has been completed.

If desired, the device may be placed into the

corresponding Idle mode during the conversion. If the

device clock frequency is less than 1 MHz, the A/D FRC

clock source should be selected.

19.2.7

ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will

wake-up

from

Sleep

when

the

conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

19.2.8

SPECIAL EVENT TRIGGER

The CCP2 Special Event Trigger allows periodic ADC

measurements without software intervention. When

this trigger occurs, the GO/DONE bit is set by hardware

and the Timer1 or Timer3 counter resets to zero.

Using the Special Event Trigger does not assure

proper ADC timing. It is the user’s responsibility to

ensure that the ADC timing requirements are met.

See Section 11.3.4 “Special Event Trigger” for more

information.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

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