PIC18F23K20-ESLASHML datasheet(267/456 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41303G-page 267

PIC18F2XK20/4XK20

19.1.6

INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

Conversion. The ADC interrupt flag is the ADIF bit in

the PIR1 register. The ADC interrupt enable is the ADIE

bit in the PIE1 register. The ADIF bit must be cleared by

software.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the global interrupt must be disabled. If the

global interrupt is enabled, execution will switch to the

Interrupt Service Routine. Please see Section 19.1.6

“Interrupts” for more information.

TABLE 19-1:

ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

19.1.7

RESULT FORMATTING

The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON2 register controls the output format.

Figure 19-2 shows the two output formats.

FIGURE 19-2:

10-BIT A/D CONVERSION RESULT FORMAT

Note:

The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC Clock Source

ADCS<2:0>

64 MHz

16 MHz

4 MHz

1 MHz

FOSC/2

000

31.25 ns(2)

125 ns(2)

500 ns(2)

2.0

s

FOSC/4

100

62.5 ns(2)

250 ns(2)

1.0

s

4.0

s(3)

FOSC/8

001

400 ns(2)

500 ns(2)

2.0

s

8.0

s(3)

FOSC/16

101

250 ns(2)

1.0

s

4.0

s(3)

16.0

s(3)

FOSC/32

010

500 ns(2)

2.0

s

8.0

s(3)

32.0

s(3)

FOSC/64

110

1.0

s

4.0

s(3)

16.0

s(3)

64.0

s(3)

FRC

x11

1-4

s(1,4)

1-4

s(1,4)

1-4

s(1,4)

1-4

s(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1:

The FRC source has a typical TAD time of 1.7

s.

These values violate the minimum required TAD time.

For faster conversion times, the selection of another clock source is recommended.

When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

ADRESH

ADRESL

(ADFM = 0)MSB

LSB

bit 7

bit 0

bit 7

bit 0

10-bit A/D Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSB

LSB

bit 7

bit 0

bit 7

bit 0

Unimplemented: Read as ‘0’

10-bit A/D Result

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