PIC18F13K50-ESLASHSS datasheet(69/422 Pages) MICROCHIP

69 / 422 page

 2010 Microchip Technology Inc.

Preliminary

DS41350D-page 69

PIC18F/LF1XK50

7.4

INTCON Registers

The INTCON registers are readable and writable

registers, which contain various enable, priority and

flag bits.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows for software polling.

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

R/W-x

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RABIE

TMR0IF

INT0IF

RABIF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked interrupts

0 = Disables all interrupts including peripherals

When IPEN = 1:

1 = Enables all high priority interrupts

0 = Disables all interrupts including low priority.

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

When IPEN = 1:

1 = Enables all low priority interrupts

0 = Disables all low priority interrupts

bit 5

TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt

0 = Disables the TMR0 overflow interrupt

bit 4

INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt

0 = Disables the INT0 external interrupt

bit 3

RABIE: RA and RB Port Change Interrupt Enable bit(2)

1 = Enables the RA and RB port change interrupt

0 = Disables the RA and RB port change interrupt

bit 2

TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared by software)

0 = TMR0 register did not overflow

bit 1

INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared by software)

0 = The INT0 external interrupt did not occur

bit 0

RABIF: RA and RB Port Change Interrupt Flag bit(1)

1 = At least one of the RA <5:3> or RB<7:4> pins changed state (must be cleared by software)

0 = None of the RA<5:3> or RB<7:4> pins have changed state

Note 1:

A mismatch condition will continue to set the RABIF bit. Reading PORTA and PORTB will end the

mismatch condition and allow the bit to be cleared.

RA and RB port change interrupts also require the individual pin IOCA and IOCB enable.

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