PIC18F4580-ESLASHML datasheet(199/490 Pages) MICROCHIP

199 / 490 page

DS39637D-page 199

PIC18F2480/2580/4480/4580

18.3.8

OPERATION IN POWER-MANAGED

MODES

In SPI Master mode, module clocks may be operating

at a different speed than when in full-power mode; in

the case of the Sleep mode, all clocks are halted.

In most power-managed modes, a clock is provided to

the peripherals. That clock should be from the primary

clock source, the secondary clock (Timer1 oscillator at

32.768 kHz) or the INTOSC source. See Section 3.7

“Clock Sources and Oscillator Switching” for

additional information.

In most cases, the speed that the master clocks SPI

data is not important; however, this should be

evaluated for each system.

If MSSP interrupts are enabled, they can wake the con-

troller from Sleep mode, or one of the Idle modes, when

the master completes sending data. If an exit from

Sleep or Idle mode is not desired, MSSP interrupts

should be disabled.

If the Sleep mode is selected, all module clocks are

halted and the transmission/reception will remain in

that state until the device wakes. After the device

returns to Run mode, the module will resume

transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

allows the device to be placed in any power-managed

mode and data to be shifted into the SPI Transmit/

Receive Shift register. When all 8 bits have been

received, the MSSP interrupt flag bit will be set and if

enabled, will wake the device.

18.3.9

EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

18.3.10

BUS MODE COMPATIBILITY

Table 18-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 18-1:

SPI BUS MODES

There is also a SMP bit which controls when the data is

sampled.

TABLE 18-2:

REGISTERS ASSOCIATED WITH SPI OPERATION

Standard SPI Mode

Terminology

Control Bits State

CKP

CKE

0, 0

0, 1

1, 0

1, 1

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on Page:

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

IPR1

PSPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

TRISA

PORTA Data Direction Register

TRISC

PORTC Data Direction Register

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

SSPCON1

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

SSPSTAT

SMP

CKE

D/A

R/W

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

Note 1: These bits are unimplemented in PIC18F2X80 devices; always maintain these bits clear.

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