56F8014 datasheet(61/124 Pages) FREESCALE

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Resets

56F8014 Technical Data, Rev. 11

Freescale Semiconductor

5.5.16.5

Reserved—Bits 4–2

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.5.16.6

Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6 Resets

5.6.1

General

5.6.2

Description of Reset Operation

5.6.2.1

Reset Handshake Timing

The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is

asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET

is released. The general timing is shown in Figure 5-19 .

Figure 5-19 Reset Interface

5.6.3

ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,

except the core IRQs with fixed priorities:

•

Illegal Instruction

•

SW Interrupt 3

•

HW Stack Overflow

•

Misaligned Long Word Access

•

SW Interrupt 2

•

SW Interrupt 1

Table 5-4 Reset Summary

Reset

Priority

Source

Characteristics

Core Reset

RST

Core reset from the SIM

RES

CLK

VAB

PAB

RESET_VECTOR_ADR

READ_ADR

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