DSP56F805 datasheet(33/56 Pages) FREESCALE

Part #	DSP56F805

Description	16-bit Digital Signal Controllers

PDF	56 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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External Bus Asynchronous Timing

56F805 Technical Data, Rev. 16

Freescale Semiconductor

Figure 3-11 External Bus Asynchronous Timing

Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and

T = Clock Period. For 80MHz operation, T = 12.5ns.

Parameters listed are guaranteed by design.

To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:

Top = Clock period @ desired operating frequency

WS = Number of wait states

Memory Access Time = (Top*WS) + (Top- 11.5)

A0–A15,

PS, DS

(See Note)

D0–D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Data In

Data Out

tAWR

tARDA

tARDD

tRDA

tRD

tRDRD

tRDWR

tWRWR

tWR

tDOS

tWRD

tWRRD

tAD

tDOH

tDRD

tRDD

DSP56F805 Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc